Modern logic analyzers commonly have a large number of input connections. For example, some prior art logic analyzers may have over one hundred input lines. These input lines are normally connected to processing circuitry which may be realized on a plurality of application specific integrated circuits (ASICs). In order to function properly, the clock signals which control the sampling and processing of the input signals must be common to all the ASICs used. This common clock signal (or reference signal) is typically an externally supplied signal, related to the frequency of the data signals to be acquired. In this method of acquisition, the data signals to be analyzed are acquired synchronously.
High speed asynchronous signal acquisition of analog signals is known from the TDS-500 digital sampling oscilloscope, manufactured by Tektronix Inc., of Wilsonville, Oreg. In that oscilloscope, a relatively very large number of samples are taken of the input waveform, asynchronously, to accurately define the shape of the waveform for processing and display.
It is herein recognized that such high speed sampling of the digital data presented to a logic analyzer would allow the analyzer to more precisely determine the location of the edges of the digital signals, thus better defining the logic states of the input digital data. It is envisioned that such a system would utilize, for example, a 250 MHz clock. Unlike the above mentioned TDS-500 oscilloscope, it is herein recognized that if both edges of that clock were utilized, the sampling rate would be effectively doubled, thus providing the benefits of a 500 MHz clock while employing a lower speed clock.
Unfortunately, two problems immediately arise. The first is, due to limitations in the number of inputs which can be handled on a typical ASIC, multiple ASICs are required. Each ASIC has literally tens of thousands of gates to be driven by the common high speed clock signal. The combined capacitances of the inputs of those gates requires the common clock signal to be amplified significantly to enable it to drive all the gates. This causes a problem because seemingly identical ASICs necessarily exhibit different delays in their internal circuitry. This unfortunate truth results in a clock signal which undesirably occurs at a different time for each ASIC. That is, the amplifier chain delays and distorts the clock signal in relation to the original input clock signal.
The second problem concerns the use of both edges of the clock. In order to do so, it is critical that the clock signal be a square wave (i.e., have equal high and low periods, that is, an equal duty cycle). Unfortunately, it is herein recognized that the amplifier chain also distorts the duty cycle of the high speed clock.
Therefore, the problem to be solved is to ensure that the final high speed clocks used in each of perhaps sixteen different ASICs are substantially identical to each other, in phase, frequency and duty cycle.